Modern chip designers, their design collaborators and their fabricators understand that chips need to have hardware capabilities exposed to the diversity of applications that will run on their designs.

The chips themselves need to be performative under a variety of potential uses and developers need to have the flexibility to cost-effectively tune these chips to their applications.

From Config’s perspective, we can improve performance at any interface of complexity with a chip if that chip is designed to interface with computational tools for goal setting and manipulation. 

That said, there are significant additional opportunities for application of Self-Aware™ capabilities as chip companies move “up-the stack” and continue to evolve a full suite of software tools for developers to apply their technology and build robust applications. 

Self-awareness expands the opportunity for chip companies to extend the “control knobs” they expose on chips to move further “up-the-stack” to the application building and operating environment to advantage diverse, application developers. Providing native access to goal manipulation up and down the stack has been shown to increase performance significantly.

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Individual Chips

Traditional chips are designed with static configurations that are optimized for specific tasks or operating conditions. Self-Aware™ computing requires chips to dynamically reconfigure themselves, which is incompatible with many existing architectures​​.

Most chips lack the necessary mechanisms to adjust configurations in real time, as they were not designed with goal-oriented adaptability in mind​​.

Yet, when provided, Self-Aware™ computing presents transformative opportunities for chips by enabling dynamic adaptability, robust performance and efficient resource use, particularly in challenging areas of increasing complexity that are otherwise difficult to configure or stabilize.

Variable configuration spaces embedded in future silicon at interfaces of complexity could use goals to extract improved control and performance from within those targeted workloads; for example, goals can easily be applied for tunable latency vs. accuracy, computing core strategies, bandwidth management and other uses.

Chip OS

Every individual chip exposes “knobs” that permit developers to use various software tools to configure the chip to best meet individual application requirements. These knobs control settings in the chips where chip designers have permitted static configuration of their chips. The process of configuring the chip at the OS level is a natural for application of Self-Aware™ computing capabilities.

Self-Aware™ computing capabilities can be applied at the OS level or anywhere up the stack at each point of complexity or potential conflict. These distributed goals can be integrated with each other or made to function narrowly at one specific managed interface. 

When goals are applied, chips become more dynamically tailored to the specific workload they are used to support. In addition to the customer, this also benefits the chip supplier who can now make standard chip families behave more like specialty chips designed for individual customer needs and performance objectives, lessen design complexity and improve speed to market. 

And goals can be changed by simply changing the goals when the situation demands a new performance target.

Chips in Computing Systems

As chips are deployed in ever more complex systems, Self-Aware™ computing opportunities expand as configuration complexity increases. For example, in Data Centers, a server or a cluster of servers have many dynamic interfaces to manage, some in the diversity of workloads shared among the compute resources, some in scheduling, some in management of mechanical systems (cooling, maintenance requirements, meeting customer SLAs, etc.) and others.

Legacy Chips

Self-Aware™ computing capabilities can improve the performance of legacy chips by permitting dynamic tuning of configuration “knobs” to goals. This capability permits legacy chips to be “modernized” at the OS level by simply modifying goals from time to time, under developer control; experience has shown that the power performance in compute/watt has improved markedly (well over 20%), without sacrifice of accuracy or latency.