Design of an Accelerator-Rich Architecture by Integrating Multiple Heterogeneous Coarse Grain Reconfigurable Arrays Over a Network-on-Chip

Read abstract

Motivation
G. Venkatesh, J. Sampson, N. Goulding, S. Gracia, V. Bryksin, J. L. Martinez, S. Swanson, M. B. Taylor, ”Conservation cores: reducing the energy of mature computations”, ASPLOS 10, pp. 205218, 2010.

  • It is shown that only a 7% of 300mm^2 die can be used at full frequency within a power budget of 80W. The un-utilized part of the chip is now-a-days called Dark Silicon. The dark silicon can be replaced with accelerators as they are not used most of the time.
  • Another motivation to propose an accelerator-rich platform is to meet an increasing demand for throughput, for example the number of spatial streams in IEEE-802.11x family of wireless standard has increased from one to eight.